The present invention relates generally to analog-to-digital conversion methods and devices, and more particularly to improvements in flash analog-to-digital conversion.
Analog-to-digital (A/D) conversion serves to transform a measured analog quantity to digital form, typically for such purposes as computer processing, digital display, or storage in data memory. Of the many different techniques available for A/D conversion, flash A/D conversion is among the fastest. The flash converter performs a simultaneous comparison that enables generating all of the bits in the binary output in parallel, unlike, for example, a successive approximation A/D converter in which the operation is performed in sequence so that a serial output is obtained running from most significant bit (MSB) to least significant bit (LSB).
Referring to FIG. 1, a typical prior art flash A/D converter 10 includes a resistor string or resistor ladder 12 which consists of a plurality of resistors that are seriesconnected between a positive voltage source (V.sub.R +) and a negative voltage source (V.sub.R -). In the circuit of FIG. 1, the resistor string is connected between +V.sub.REF and circuit ground. At taps between each pair of the resistors a circuit connection is made to the negative input of a respective comparator of a plurality of operational amplifier comparators 15 numbering one less than the number of resistors in the string, the string thus constituting a resistive voltage-divider circuit. The negative input to each comparator is therefore a reference voltage whose value depends on the position or connection of the respective comparator in the resistor string.
In general, the number of comparators required for conversion to an n-bit binary code is equal to 2.sup.n -1, i.e., 2.sup.n -1 intermediate states exist for 2.sup.n binary states, and for every intermediate state there is an associated comparator which must be used for evaluation of the analog quantity. Thus, an 8-bit flash A/D converter offers extremely fast conversion time, but requires 2.sup.8 -1=256-1=255 comparators, which represents a considerable challenge in implementation from the standpoint of device size. In the flash A/D converter 10 depicted in FIG. 1, n=3 so that only 8-1=7 comparators are needed.
The positive input to each comparator is the analog input voltage to be converted to digital format, and is common to each of the comparators. When the analog input voltage exceeds the reference voltage for a particular comparator the comparator will generate a high. The output of each of the comparators 15, representing the eight bits to be converted, is connected to a respective input of a binary encoder 17, according to the position of the comparator along the resistive divider. Thus, comparator 18, which is positioned in the voltage divider circuit to receive the largest percentage of reference voltage +V.sub.REF relative to the other comparators, is connected to input 7 of encoder 17, while comparator 20, which has the smallest percentage of the reference voltage applied to it, is connected to input 1 of encoder 17.
Encoder 17 is a "priority" encoder, so-called because its parallel 3-bit binary output code is determined by the highest order input that is a high (i.e., a "1"). For example, if the analog input voltage exceeds the reference voltage at comparator 21 but not at any comparator above 21 on the resistive divider at the time a sampling pulse is applied to the enable input EN of encoder 17, then comparator 21 and every comparator below 21 on the resistive divider will generate a high. But no comparator above 21 will go high. In this example, then, encoder 17 will generate a binary code of 101 (i.e., equal to 5 in the decimal system), because the 5 input attributable to comparator 21 is the highest order input with a high output.
Not only is the A/D conversion of the flash converter extremely fast, but an analog signal can be converted to digital format with relatively high resolution if the sampling rate is high. These advantages tend to offset to some degree the disadvantage of the large number of comparators required for a high accuracy readout. But the device suffers from another significant drawback, namely, its relatively heavy power consumption with the multiplicity of comparators and encoder which are typically implemented on a semiconductor integrated circuit chip, for which low power dissipation is the desired status.
It is therefore a principal aim of the present invention to provide a flash A/D converter that affords considerable power saving over converters of that type heretofore available.